Senior at UIUC focused on microarchitecture, RTL design, and next-generation accelerator architectures.
I am a senior Computer Engineering student at UIUC specializing in RTL design, ASIC development, and accelerator microarchitecture, with coursework spanning computer organization, logic synthesis, parallel programming, and algorithms. I’ve applied this expertise as an ASIC Design Intern at NVIDIA, a Hardware Research Assistant at PlatformX extending GPGPU-Sim, and a Course Staff member for ECE 411 mentoring students on out-of-order RISC-V processors. In software, I interned at CME Group, leading teams on deployment monitoring and low-latency trading algorithms, and at Aechelon Technology, optimizing GPU kernels and real-time media streaming. Beyond industry, I actively contribute to the UIUC tech community, tutoring peers through Eta Kappa Nu, organizing events as ACM Social Chair, and facilitating architecture discussions with SIGArch, combining technical skill, mentorship, and leadership. You can reach me at saipranavvk@gmail.com